Increased datacenter traffic is stretching the upper bound capability of electronic packet switching. Photonic switching is a potential solution. However, standalone photonic switches are typically relatively small in size. On the other hand, practical core switches may require design for tens of terabits (Tb) throughput. Photonic core switches should match this capacity if they are to be deployed. Currently, the switches that can be built in silicon photonic circuits are 4×4 and 8×8. This may not be enough capacity given that with an interface rate of 100 Gbps (Gigabits per second) the throughput is 0.8 Tbps (Terabits per second). Core switch capacity should scale to tens of terabit for such capacity deployment. As a result, silicon photonic switches should scale to 50 Tbps or higher to be comparable to their electrical counterpart. There is a need for improved scalable photonic packet architectures with photonic integrated circuit (PIC) switches to meet such requirements.